1. Field of the Invention
The present invention relates to digital-to-analog converters (DACs) in general and in particular to DACs which can be switched between a sleep mode and a normal operating mode in high speed, e.g. 100 mHz, video graphics systems employing pipeline architecture with little, if any, surge current resulting therefrom.
2. Description of the Prior Art
A conventional color video graphics system, e.g. color palette, comprises three DACs for driving the red, green and blue analog inputs of a typical color monitor. Each of the DACs may comprise as many as 400 stages depending on the desired resolution of the DAC. Using conventional CMOS technology, each stage typically comprises three CMOS field-effect (FET) transistors, e.g. a bias transistor, a reference voltage transistor and a digital input transistor.
In normal operation, a current flows in each of the stages of a conventional CMOS DAC at all times, even when the DAC is not being used. The power thus consumed is a serious impediment to the use of such DACs in battery powered video graphics systems, such as lap top computers.